VerifSudha has been laser focused on how to improve functional verification quality for last two years.  You can read about our journey through 100+ blogs published.

Using this expertise and insights we have built our framework “curiosity” for constrained random stimulus quality analysis by generating whitebox  functional  and statistical coverage. This framework is embodiment of several man years of verification expertise.

To help you realize the benefits of this framework quickly we offer following services.

Whitebox functional and statistical coverage generation service

We found that often reason for not writing whitebox functional coverage is lack of time.

Whitebox coverage can provide very interesting insights about your IP level constrained random stimulus quality. Many critical bugs hide at intersection of requirements and micro-architecture specification. These can be uncovered through whitebox coverage.

We have built framework that can semi-automatically generate the whitebox functional and statistical coverage for your design.

We offer service to generate whitebox functional and statical coverage for your RTL design, integrate it in your verification environment, run your regressions and reports results 3x-5x faster over manually doing it.

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PCIe PIPE Functional coverage model

For simple interface integration, the toggle coverage may be sufficient but not for the PIPE interface.

For PIPE interface to be completely exercised, it must be covered with:

  • Toggling of signals in all supported speeds
  • Sequence of events
  • Variation in timing
  • Concurrency of functional group of signals
  • Multiple lanes
  • Key events taking place multiple times

We have a built a comprehensive and configurable functional coverage model for PIPE interface. Model covers following areas with 80+ SystemVerilog coverpoints:

We offer service to integrate our coverage model into your test bench, customize and help you close the coverage holes found.

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For complete functional coverage plan and demo, please email: